Video Timing Calculator – VGA/HDMI Pixel Clock & Porches

Mode

Resolution & timing

Width (px)

Height (px)

Refresh (Hz)

Interlaced

▢

Enter resolution and refresh rate, then click Calculate.
Or select a standard preset from the dropdown above.

Standard video modes — click Use to load into calculator

Standard	Mode	Pixel clock	H total	H FP	H sync	H BP	V total	V FP	V sync	V BP	H pol	V pol	Scan

Analog RGB — VGA (VESA, 75 Ω termination)

RGB channel voltage levels

Level	Voltage	IRE
White (100%)	+0.700 V	100 IRE
Mid-grey (50%)	+0.350 V	50 IRE
Black / Blanking	0.000 V	0 IRE

Signal source impedance: 75 Ω (driver) into 75 Ω (monitor).
Open-circuit output from FPGA DAC: 1.4 V peak (voltage divider halves it at load).
During Front Porch, Sync pulse and Back Porch: RGB must be strictly 0.000 V. Monitor uses Back Porch for DC restoration / black-level clamping — any non-zero voltage shifts the black point causing grey or colour-shifted image.

RGB waveform — one line (H axis = time)

H-SYNC / V-SYNC — VGA (TTL, separate wires)

State	Voltage	TTL level
Idle (inactive)	3.3 V / 5.0 V	Logic HIGH
Sync pulse (active)	0.0 V	Logic LOW
Monitor threshold LOW	< 0.8 V	guaranteed LOW
Monitor threshold HIGH	> 2.0 V	guaranteed HIGH

These are digital TTL signals — no 75 Ω termination, no analogue levels.
FPGA I/O pins drive them directly (3.3 V LVCMOS or 5 V TTL buffer).
Polarity (positive/negative) is standard-defined — see timing presets.

HSYNC waveform — negative polarity (e.g. VGA 640×480)

Composite Video (CVBS) & Sync-on-Green (SOG) — 1.0 V_p-p / 75 Ω

Level	Voltage	IRE	Notes
White	+0.700 V	+100	both PAL & NTSC
Black (PAL)	0.000 V	0	no pedestal
Black (NTSC)	+0.054 V	+7.5	setup / pedestal
Blanking	0.000 V	0	FP, BP, guard bands
Sync tip	−0.300 V	−40	below black, into negative
Total swing	1.000 V_p-p	140	sync tip to white
Colour burst (PAL)	±0.150 V	±21	4.433 MHz on back porch
Colour burst (NTSC)	±0.143 V	±20	3.579 MHz on back porch

SOG (Sync-on-Green): sync pulse at −0.3 V is mixed directly into the Green channel. Used in professional RGB-BNC monitors (SGI, Sun), some industrial displays and HD component (RGBHV → RGBS). Requires AC-coupled or negative-voltage-capable output stage.

Composite / SOG waveform — one line

Component Video — Y/Pb/Pr (ITU-R BT.601 / BT.709)

Y — Luma (+ sync)

White	+0.700 V
Black	0.000 V
Sync tip	−0.300 V
1.0 V_p-p total, 75 Ω

Pb — Blue difference

Max positive	+0.350 V
Centre (zero)	0.000 V
Max negative	−0.350 V
0.7 V_p-p (±350 mV), 75 Ω

Pr — Red difference

Max positive	+0.350 V
Centre (zero)	0.000 V
Max negative	−0.350 V
0.7 V_p-p (±350 mV), 75 Ω

Y carries sync (same as composite). Pb and Pr are bipolar — zero volts = no colour difference (grey). During blanking Pb = Pr = 0 V. BT.601 = SD (480i/576i), BT.709 = HD (720p/1080i/1080p), BT.2020 = UHD — same voltage levels, different colour matrix.

Digital interfaces — HDMI / DVI / DisplayPort / LVDS

HDMI / DVI — TMDS (differential)

Parameter	Value
Signalling	Differential (TMDS)
Differential swing	200 – 600 mV_p-p
Common mode voltage	2.8 – 3.1 V
Termination	100 Ω differential
Channels	3× data + 1× clock
HDMI 1.4 max rate	3.4 Gbps / channel
HDMI 2.0 max rate	6.0 Gbps / channel
HDMI 2.1 max rate	12.0 Gbps / channel (FRL)
Encoding	TMDS 8b/10b (≤2.0), FRL (2.1)
Standard	CTA-861, HDMI spec 1.4/2.0/2.1

HDMI carries no separate sync wires — H/V sync is embedded in the TMDS data stream as a control period between active video packets. Pixel data, audio, and metadata travel in the same differential pairs.
TMDS uses CML (Current Mode Logic): the sink terminates each line with 50 Ω to V_AVCC = +3.3 V, so V_CM = V_AVCC − V_swing/2 ≈ 2.8–3.1 V. Driving HDMI with a 1.2 V common-mode output (LVDS levels) will not establish a link.

DisplayPort & LVDS / eDP (panel interfaces)

Interface	Swing	Notes
DisplayPort 1.4	0.4 / 0.6 / 0.8 V	selectable, diff, 100 Ω
DP 1.4 max rate	8.1 Gbps / lane	HBR3, 4 lanes
LVDS (FPD-Link)	250 – 450 mV_p-p	diff, 100 Ω, ≤ 135 MHz
LVDS common mode	~1.2 V	TIA/EIA-644
eDP (embedded DP)	0.4 / 0.6 / 0.8 V	laptop panels, diff
MIPI DSI	100 – 300 mV_p-p	mobile/embedded LCD

All digital panel interfaces use differential pairs — no ground-referenced analogue levels. No sync voltage concept: data is serialised with embedded clock or separate clock pair. FPGA typically uses dedicated SERDES or LVDS I/O banks.
DisplayPort main link is mandatorily AC coupled — series capacitors (75–200 nF) on the transmitter side block DC, so the transmitter common-mode level is irrelevant to the receiver. This is in contrast to HDMI/TMDS where the DC common-mode must match the sink's CML termination voltage (~3.3 V).

Standards reference

Standard	Covers	Interface / signal type	Key levels
VESA VGA spec	640×480 and all VGA modes	Analog RGB + TTL sync	0–0.7 V / 0–5 V TTL
ITU-R BT.601	SD colour matrix 480i/576i	Y/Pb/Pr analogue + digital	Y: 1.0 Vp-p / Pb,Pr: ±0.35 V
SMPTE 253M	YPbPr component analogue interface	Y/Pb/Pr analogue, RCA / BNC	Y: 1.0 Vp-p (sync incl.) / Pb,Pr: ±0.35 V, 75 Ω
ITU-R BT.709	HD colour matrix 720p/1080i/p	Y/Pb/Pr analogue + digital	same levels as BT.601, HD colour matrix
ITU-R BT.2020	UHD 4K/8K colour	digital (HDMI/DP)	same levels, wider colour gamut
SMPTE 170M	NTSC composite	CVBS analogue, 75 Ω	1.0 Vp-p, sync −0.3 V, pedestal +7.5 IRE
ITU-R BT.470	PAL / SECAM composite	CVBS analogue, 75 Ω	1.0 Vp-p, sync −0.3 V, no pedestal
SMPTE 274M	HD-SDI 1080 series	Serial digital, 75 Ω coax	800 mVp-p, 10-bit
CTA-861 (CEA)	HDMI/DVI video formats	TMDS digital differential	200–600 mVp-p diff, 100 Ω
VESA DisplayPort	DisplayPort 1.x / 2.x	Differential serial, 100 Ω	0.4 / 0.6 / 0.8 Vp-p selectable
TIA/EIA-644	LVDS (generic)	Differential, panel link	250–450 mVp-p diff, ~1.2 V CM
MIPI DSI	Mobile / embedded panels	Differential serial	100–300 mVp-p diff

CVBS requires a 1.0 V_p-p swing with sync tip at −0.3 V (below black). Since a unipolar DAC cannot go negative, the signal is shifted +0.3 V (sync tip → 0 V) and AC-coupled to the load. The TV's DC restorer re-clamps the sync tip back to −0.3 V internally. The op-amp gain and DAC counts depend on your DAC reference voltage — configure below.

DAC configuration

DAC V_ref (full-scale)

Custom V_ref (V)

Op-amp gain

DAC resolution

Op-amp gain: — · DAC utilisation: —

DAC level mapping

Signal level	CVBS std.	DAC out	DAC count

Formula: DAC = round((V_cvbs + 0.3) / V_ref × (2ⁿ − 1))
PAL colour burst: 4.43361875 MHz sinusoid, ±0.150 V around black level.

DAC output waveform — one line (shifted +0.3 V)

Output hardware topology — video buffer with AC coupling

① DAC output

0 – 1 V

shifted waveform
sync=0 V, white=1 V

② Video op-amp

Av = 2×

THS7314 / ADA4851
output: 0 – 2 V

③ Series resistor

RS = 75 Ω

source termination
impedance match

④ AC coupling

220–470 µF

electrolytic + 100 nF
ceramic (burst)

      DAC(0–1V) ──┬── Op-Amp(Av=2) ── 75Ω ──┬── C(220µF+100nF) ──── RCA/BNC ──── TV (75Ω load)
                   │                           │
                   └── Rf/Rg (gain set)       └── V_out = (0–2V)/2 = 0–1V
    

The TV's 75 Ω load forms a voltage divider with R_S: V_TV = V_opamp × 75/(75+75) = (0–2 V)/2 = 0–1 V — back to the correct CVBS swing.
AC coupling removes the 0.3 V DC offset. The TV's DC restorer / clamping circuit on the composite input re-references the signal so that sync tip = −0.3 V internally.
Electrolytic capacitor orientation: positive pole toward the op-amp output (the DC level before the cap is positive). Parallel 100 nF ceramic ensures colour burst (4.43 MHz) passes without attenuation.

DAC / pixel clock sampling rates for PAL CVBS

Pixel clock	Samples / burst cycle	Burst samples / line	Suitability
8.867 MHz	2.00	~18	Nyquist minimum — poor quality
13.500 MHz	3.05	~27	ITU-R BT.601 standard — usable
17.734 MHz	4.00	~54	4× subcarrier — integer ratio, ideal
27.000 MHz	6.09	~54	2× BT.601 — recommended, easy filter
35.469 MHz	8.00	~108	8× subcarrier — high quality

PAL colour burst parameters

Subcarrier frequency	4.43361875 MHz
Exact value	283.75 × f_H + 25 Hz
Burst amplitude	±0.150 V (±21 IRE)
Burst position	Back porch, ~9 cycles
Burst start (after sync)	~5.6 µs after H-sync leading edge
PAL phase alternation	V component flips ±90° each line
NTSC burst freq.	3.57954545 MHz

17.734 MHz = 4 × f_sc gives an exact integer ratio — burst samples repeat with a fixed phase pattern, simplifying the lookup table. At 13.5 MHz the fractional ratio (3.0459…) means the burst phase drifts across lines and requires a continuous phase accumulator.

Code constants — DAC values (C / FPGA)

/* PAL CVBS DAC constants — 0-1V output, +0.3V offset, AC coupled */
/* Formula: DAC = round((V_cvbs + 0.3) / 1.0 * (MAXVAL))          */

/* 8-bit DAC (0–255) */
#define PAL_8_SYNC_TIP     0    /* -0.300 V */
#define PAL_8_BURST_LO    38    /* -0.150 V (burst trough) */
#define PAL_8_BLACK       77    /*  0.000 V */
#define PAL_8_BURST_HI   115    /* +0.150 V (burst peak) */
#define PAL_8_WHITE      255    /* +0.700 V */

/* 10-bit DAC (0–1023) */
#define PAL_10_SYNC_TIP    0
#define PAL_10_BURST_LO  153
#define PAL_10_BLACK     307
#define PAL_10_BURST_HI  460
#define PAL_10_WHITE    1023

/* 12-bit DAC (0–4095) */
#define PAL_12_SYNC_TIP    0
#define PAL_12_BURST_LO  614
#define PAL_12_BLACK    1229
#define PAL_12_BURST_HI 1843
#define PAL_12_WHITE    4095

/* PAL subcarrier */
#define PAL_SUBCARRIER_HZ  4433618UL   /* 4.43361875 MHz */
#define PAL_BURST_CYCLES   9           /* cycles per line */

-- PAL CVBS DAC constants — 0-1V output, +0.3V offset, AC coupled
-- Formula: DAC = round((V_cvbs + 0.3) / 1.0 * (2^N - 1))

package pal_cvbs is

  -- 8-bit DAC (0–255)
  constant PAL_8_SYNC_TIP  : integer :=   0;  -- -0.300 V
  constant PAL_8_BURST_LO  : integer :=  38;  -- -0.150 V burst trough
  constant PAL_8_BLACK     : integer :=  77;  --  0.000 V
  constant PAL_8_BURST_HI  : integer := 115;  -- +0.150 V burst peak
  constant PAL_8_WHITE     : integer := 255;  -- +0.700 V

  -- 10-bit DAC (0–1023)
  constant PAL_10_SYNC_TIP : integer :=    0;
  constant PAL_10_BURST_LO : integer :=  153;
  constant PAL_10_BLACK    : integer :=  307;
  constant PAL_10_BURST_HI : integer :=  460;
  constant PAL_10_WHITE    : integer := 1023;

  -- 12-bit DAC (0–4095)
  constant PAL_12_SYNC_TIP : integer :=    0;
  constant PAL_12_BURST_LO : integer :=  614;
  constant PAL_12_BLACK    : integer := 1229;
  constant PAL_12_BURST_HI : integer := 1843;
  constant PAL_12_WHITE    : integer := 4095;

  -- PAL subcarrier
  constant PAL_SUBCARRIER_HZ : integer := 4_433_618;  -- 4.43361875 MHz
  constant PAL_BURST_CYCLES  : integer := 9;

end package pal_cvbs;

// PAL CVBS DAC constants — 0-1V output, +0.3V offset, AC coupled
// Formula: DAC = round((V_cvbs + 0.3) / 1.0 * (2^N - 1))

// 8-bit DAC (0–255)
parameter PAL_8_SYNC_TIP  =   0;  // -0.300 V
parameter PAL_8_BURST_LO  =  38;  // -0.150 V burst trough
parameter PAL_8_BLACK     =  77;  //  0.000 V
parameter PAL_8_BURST_HI  = 115;  // +0.150 V burst peak
parameter PAL_8_WHITE     = 255;  // +0.700 V

// 10-bit DAC (0–1023)
parameter PAL_10_SYNC_TIP =    0;
parameter PAL_10_BURST_LO =  153;
parameter PAL_10_BLACK    =  307;
parameter PAL_10_BURST_HI =  460;
parameter PAL_10_WHITE    = 1023;

// 12-bit DAC (0–4095)
parameter PAL_12_SYNC_TIP =    0;
parameter PAL_12_BURST_LO =  614;
parameter PAL_12_BLACK    = 1229;
parameter PAL_12_BURST_HI = 1843;
parameter PAL_12_WHITE    = 4095;

// PAL subcarrier
parameter PAL_SUBCARRIER_HZ = 4_433_618;  // 4.43361875 MHz
parameter PAL_BURST_CYCLES  = 10;  // 10 × 225.5 ns = 2.255 µs (ITU-R BT.470 centre)