Common-Emitter NPN BJT Amplifier

DC bias · node voltages · operating region · small-signal AC model · voltage gain · impedances · input swing limits

This analyzer takes a common-emitter NPN stage with a selectable topology (base divider with or without R2, emitter resistor with optional bypass capacitor, input coupling capacitor, and a resistive or inductor/RFC collector load) and computes the DC operating point, node voltages, transistor operating region, small-signal gain from the hybrid-π model, input/output impedances, maximum undistorted swing, and the lower −3 dB frequency set by the coupling and bypass capacitors.

0Circuit configuration

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Circuit Schematic

1Parameters

Transistor and supply
Typically 0.60–0.70 V
Saturation threshold
Base bias network
Collector load
Emitter
Analysis frequency
Used for: Cb and CE reactances, inductor XL, lower −3 dB cutoff checks

Formula Reference

Thevenin equivalent of base divider:
V_th = V_CC · R2 / (R1+R2) [open-circuit voltage]
R_th = R1 ‖ R2 = R1·R2/(R1+R2) [Thevenin resistance]
Single R1 only: V_th = V_CC, R_th = R1
Exact BJT emitter current (one formula, all cases):
I_E = (V_th − V_BE) / (R_E + R_th/(β+1))
I_C = I_E · β/(β+1)
I_B = I_C / β
Note: includes I_B loading of divider – no approximation
Node voltages:
V_E = I_E · R_E
V_B = V_E + V_BE (actual, under I_B load)
V_C = V_CC − I_C · R_C (resistor load)
V_C = V_CC (inductor/RFC load, DC drop ≈ 0)
V_CE = V_C − V_E

Small-signal parameters (at Q-point):
g_m = I_C / V_T, where V_T = 26 mV at 25 °C
r_e = 1/g_m = V_T / I_C [emitter resistance]
r_π = β / g_m = β · r_e [base-emitter resistance]
Emitter impedance at frequency f:
No C_E: Z_E = R_E (full emitter degeneration)
With C_E: Z_E = R_E ‖ (1/jωC_E) → |Z_E| = R_E / √(1 + (ωC_E·R_E)²)
At f >> f_CE: |Z_E| → 0 (C_E effectively shorts R_E)
Effective transconductance with emitter degeneration:
g_m,eff = g_m / (1 + g_m · |Z_E|)
Voltage gain: A_v = −g_m · Z_C / (1 + g_m · |Z_E|) = −g_m,eff · Z_C
(negative sign = phase inversion)

Input impedance at base node:
Z_in,base = r_π + (β+1) · |Z_E| [looking into base]
With R1‖R2 bias: Z_in,amp = R1 ‖ R2 ‖ Z_in,base
With R1 only: Z_in,amp = R1 ‖ Z_in,base
Effect of coupling capacitor C_b:
X_Cb = 1/(ω·C_b) at analysis frequency f
Signal at base = V_source · Z_in / √(Z_in² + X_Cb²)
Low-frequency cutoff: f_Cb = 1/(2π·C_b·Z_in,amp)
Output impedance (simplified, r_o = ∞):
Z_out = R_C (resistive load)
Z_out = jω·L → |Z_out| = ω·L (inductive load at f)

Saturation limit (positive input → output clips low):
Δi_C,sat = (V_CE,Q − V_CE,sat) / Z_C [max increase before V_C = V_CE,sat + V_E]
v_in,sat = Δi_C,sat · (1/g_m + |Z_E|) [input amplitude that causes saturation]
v_out,sat = V_CE,Q − V_CE,sat [output negative peak]
Cutoff limit (negative input → output clips high):
Δi_C,cut = I_C,Q [max decrease before I_C = 0]
v_in,cut = I_C,Q · (1/g_m + |Z_E|) [input amplitude that causes cutoff]
v_out,cut = I_C,Q · Z_C [output positive peak]
(For RFC: can swing up to ~V_CE,Q above quiescent via stored energy)
Maximum undistorted symmetric swing:
v_in,max = min(v_in,sat, v_in,cut) [peak input, smaller of both limits]
v_out,max = min(v_out,sat, v_out,cut) [peak output]
Optimal Q-point: I_C,opt = (V_CC − V_E − V_CE,sat) / (2·R_C) → equal swings

C_b coupling pole (high-pass at input):
f_Cb = 1 / (2π · C_b · Z_in,amp)
C_E bypass pole (emitter degeneration removed above f_CE):
R_th,E = (r_π + R_th,bias) / (β+1) [resistance seen at emitter]
f_CE = 1 / (2π · C_E · (R_E ‖ R_th,E))
Above f_CE: gain rises from −R_C/R_E toward −g_m·R_C
Dominant lower pole:
f_low = max(f_Cb, f_CE) [whichever is higher determines −3 dB]