CR Phase-Shift Oscillator Calculator

Design tool for 3-stage CR phase-shift network oscillators

This calculator computes the oscillation frequency and loop gain of a 3-stage RC phase-shift network (C1-R1, C2-R2, C3-R3, series C with shunt R to AC ground at each node) combined with an inverting BJT amplifier. It offers a quick mode for equal R/C values, a numerical solver for arbitrary component values with optional load resistance, and a step-by-step guide for designing the DC bias point, AC gain, base bias network and coupling/bypass capacitors of the transistor stage.

This tool models a 3-stage CR phase-shift network: C1-R1, C2-R2, C3-R3 (series C, shunt R to AC ground at each node). The inverting amplifier (~180°) combined with the CR network (~180°) creates the required 360° loop phase shift for oscillation.

CR Phase-Shift Oscillator Block Diagram

Note: In BJT circuits, resistors can connect to either GND or +Vcc. For AC analysis with proper supply decoupling, both are equivalent AC ground.

Quick Design (Equal Components: C1=C2=C3=C, R1=R2=R3=R)

C (value)

C (unit)

f0 (Hz)

Note: For this topology: f0 = 1 / (2πRC√6) and |β| = 1/29 at oscillation point.

Advanced Numerical Solver (Arbitrary C/R Values + Optional Load)

Enter C1-C3 and R1-R3. Optionally specify Rin (amplifier input resistance) at the output node. The solver numerically finds the frequency where the network phase ≈ -180°, then calculates |β| and minimum |A|.

C1 (nF)

C2 (nF)

C3 (nF)

R1 (Ω)

R2 (Ω)

R3 (Ω)

Rin (Ω; 0 = ignore)

fMin (Hz)

fMax (Hz)

Scan Points

Phase Tolerance (°)

Evaluate H(jω) at specific frequency (Hz)

Step-by-Step BJT Oscillator Design Guide

Complete design procedure for CR phase-shift oscillator with BJT amplifier

Complete BJT CR Phase-Shift Oscillator Circuit

Step 1: CR Network Design (Frequency Selection)

Theory (Asymmetric Network):
This design uses only 2 phase-shift resistors (R2, R3) + bias network as 3rd stage!
Starting point (symmetric): f₀ = 1 / (2π·R·C·√6)
We calculate R for stages 1 & 2: R = 0.0650 / (f₀·C)

Stage 3 uses Rin_total (calculated in Step 4):
Rin_total = (R1_bias || R2_bias) || Rin_base
where Rin_base = r_π + (β+1)·RE1 is the transistor base input impedance.

Network is asymmetric (R2 ≈ R3 ≈ R, but Rin_total typically 2-5× larger)
Actual f₀ and β will be calculated numerically in Step 6 with real Rin_total value.

Target frequency f₀ (Hz)

Choose C (nF) Typical: 4.7nF - 100nF

Step 2: DC Operating Point Design

Theory:
Choose DC operating point for maximum output swing:
• Vcc - supply voltage (typically 5-12V)
• Ic - collector current (0.5-5 mA for small signal)
• Vc ≈ Vcc/2 - collector voltage (headroom for sine wave)
• Ve ≈ 0.6-1.5V - emitter voltage (DC stability)

Component calculation:
• RC = (Vcc - Vc) / Ic
• RE_total = Ve / Ic

Vcc (V)

Ic (mA)

Vc (V) ≈ Vcc/2

Ve (V) 0.6-2V

Step 3: AC Gain Design (with dynamic resistance r_e)

Theory:
To achieve gain ≥29, use split emitter configuration:
• RE1 - unbypassed (sets AC gain)
• RE2 - bypassed with capacitor CE (maintains DC current)
• RE1 + RE2 = RE_total (from Step 2)

Dynamic emitter resistance (critical parameter!):
• r_e = VT / Ie ≈ 26mV / Ie
• VT = 26mV is thermal voltage at 25°C (from kT/q)
• This is NOT Vbe! (Vbe ≈ 0.6-0.7V is DC junction voltage)

AC gain:
• |A| ≈ RC / (RE1 + r_e)
• For |A| ≈ 40: RE1 ≈ RC/40 - r_e

Base input resistance (used in Step 4 for accurate Rin):
• Transconductance: g_m = Ic / VT
• Base-emitter resistance: r_π = β / g_m
• Base input impedance: Rin_base = r_π + (β+1)·RE1
This parameter is critical for accurate CR network loading calculation!

Target gain |A| Recommended 35-50

β (hFE) Typical: 100-300

RC from Step 2 (Ω)

Ic from Step 2 (mA)

Step 4: Base Bias Network Design

Theory:
Voltage divider R1 (Vcc→base) and R2 (base→GND) sets base operating point:
• Vb ≈ Ve + 0.65V (B-E junction drop)
• Divider current: typically Idiv ≈ 10×Ib (for stiff divider)
• For hFE≈100-200: Ib = Ic/hFE ≈ Ic/150
• Choose Idiv ≈ 0.1mA (compromise)

Calculation:
• R1 + R2 = Vcc / Idiv
• R2 / (R1+R2) = Vb / Vcc
• R2 = (R1+R2) × Vb/Vcc
• R1 = (R1+R2) - R2

Total input impedance for CR network loading:
The CR network is loaded not only by the bias divider, but also by the transistor base input resistance.
• Bias contribution: Rin_bias = R1_bias || R2_bias
• Base contribution: Rin_base = r_π + (β+1)·RE1 (from Step 3)
• Total: Rin_total = Rin_bias || Rin_base

Ve from Step 2 (V)

Vcc from Step 2 (V)

Divider current (mA)

Step 5: Capacitor Design

Theory:
1) Emitter bypass CE:
To bypass RE2 effectively at f₀:
• Xc = 1/(2π·f₀·CE) ≤ RE2/10
• CE ≥ 10/(2π·f₀·RE2)
Recommended: 10-47µF electrolytic

2) Output coupling C4:
For DC blocking and AC transfer:
• Typically C4 ≥ 10µF

3) Supply decoupling:
• 100nF ceramic + 47µF electrolytic as close to transistor as possible
• Prevents oscillations and ensures AC ground for +Vcc

f₀ from Step 1 (Hz)

RE2 from Step 3 (Ω)

Step 6: Output Amplitude Calculation & Final Analysis

Theory:
Maximum output amplitude (peak-to-peak):
• Limited by supply voltage and operating point
• For sinusoidal oscillation: Vout_pp ≤ 2 × min(Vc, Vcc-Vc)
• Practical: approx 70-80% of theoretical max (due to nonlinearity, distortion)

Actual amplitude:
• Vout_peak = 0.75 × min(Vc, Vcc-Vc)
• Vout_pp = 2 × Vout_peak
• Vout_rms = Vout_pp / (2√2) ≈ Vout_pp / 2.828

Gain verification with startup margin:
• Network attenuates by β_actual (numerically calculated with Rin_total loading)
• Amplifier gain is |A| (from Step 3)
• Loop gain: |A·β|
• Minimum (theoretical): |A·β| ≥ 1.0
• Recommended (practical): 1.3 ≤ |A·β| ≤ 1.5 for reliable startup without excessive distortion

Theory & Formulas

Barkhausen Oscillation Criterion

Oscillation occurs when:
1) |A · β| ≥ 1 (loop gain ≥ 1)
2) phase(A · β) = 0° = -360° (positive feedback)

Where A is the amplifier gain and β is the CR network transfer coefficient. The inverting amplifier contributes ~180°, the CR network contributes another ~180° → total phase shift -360° = 0°.

Equal Components (C1=C2=C3=C, R1=R2=R3=R)

Oscillation Frequency:
f₀ = 1 / (2π·R·C·√6) ≈ 0.0650 / (R·C)

Feedback Factor at Oscillation:
β(f₀) = -1/29 → |β| = 1/29 ≈ 0.0345

Minimum Amplifier Gain:
|A|min = 1/|β| = 29

Practical Recommendation: Design amplifier with gain |A| ≈ 35-50 to ensure reliable start-up. Excessive gain causes distortion; amplitude settles due to nonlinear mechanisms (saturation, clipping).

CR Network Topology

The CR network consists of series capacitors with shunt resistors to AC ground at each node. In BJT implementations, resistors can connect to either GND or +Vcc - with proper supply decoupling, both are equivalent AC ground.

General Case (Arbitrary Components)

For arbitrary values of C1, C2, C3, R1, R2, R3, the transfer function H(jω) = β(jω) is computed by solving the admittance equations using nodal analysis and Gaussian elimination with partial pivoting.

Numerical Algorithm

Logarithmic Scan: Searches frequency range [fMin, fMax] with N logarithmically-spaced points
Phase Detection: Finds frequency where arg(H(jω)) ≈ -180° (within tolerance ±3°)
Golden Section Refinement: Refines found frequency using golden-section search to precision ~10⁻⁶
Calculation: At found frequency f₀, computes |β| = |H(jω₀)| and minimum gain |A|min = 1/|β|

Design Considerations

Amplitude Stability: Amplitude settles via nonlinearities (transistor saturation, supply rail limits). For clean sine output, use AGC (incandescent lamp, thermistor) or soft limiting (diode pair).
Component Selection: Higher R and C → lower frequency. Typical: R = 10kΩ-100kΩ, C = 1nF-100nF for f = 100Hz-10kHz.
Tolerance: Real components have ±5% to ±20% tolerance. Actual frequency may differ ±10-20% from calculation. Use trimmers for fine-tuning.
Loading: Low amplifier output impedance is beneficial. High load impedance minimally affects transfer.
Temperature Drift: Resistors and capacitors drift with temperature. Use temperature-stable components (NPO/C0G ceramics, metal-film resistors) for critical applications.