NPN Transistor Amplifier Calculator

Common Emitter Amplifier Design and Analysis

This tool designs a common-emitter NPN amplifier stage from target specifications (supply voltage, input/output signal levels, minimum frequency, source impedance, collector current, quiescent VCE and β), computing bias divider resistors, RC, RE1/RE2, and coupling/bypass capacitor values. Two additional modes let you verify an existing circuit: Mode 1 from measured node voltages and known resistors, and Mode 2 from resistor values only (theoretical operating point and gain).

Common Emitter NPN Amplifier Circuit

+Vcc R1 Vb R2 RC Vc Q1 RE1 Ve RE2 CE
DESIGN INPUTS

Complete Amplifier Design

Workflow: Specify all requirements below, then click "Calculate Complete Design" to get all component values and design parameters.
1System Requirements
For all capacitors
Typical: 50Ω (RF), 600Ω (audio), 0Ω (ideal)
2Operating Point Choice
Typical: 1-5 mA
Recommend: VCC/2
Typical: 100-300
3AC Design Parameters
Large (>100kΩ) if unloaded

Verification and Analysis Tools

Mode 1: Calculate from Measured Voltages and Resistors

Enter measured voltages and resistor values. Calculator will compute operating point and gain.

Supply Voltage

Measured Voltages

Circuit Resistors

Mode 2: Theoretical Calculation from Resistors (without measurements)

Enter resistor values and Vcc. Calculator will predict operating point and gain.

Calculation Formulas Reference

Required Voltage Gain:
|Av| = Vout,pp / Vin,pp

Collector & Emitter Currents:
Ie = Ic · (β + 1) / β
Ib = Ic / β
Operating Point Voltages:
Ve = 1.5 V (recommended for stable biasing)
Vb = Ve + Vbe (where Vbe ≈ 0.65 V)
Vc = Ve + VCE,Q
Collector Resistor:
RC = (Vcc - Vc) / Ic
Total Emitter Resistor:
RE,total = Ve / Ie = RE1 + RE2
Bias Divider (stiff divider rule):
I_divider = 10 × Ib
R1 = (Vcc - Vb) / I_divider
R2 = Vb / I_divider
Output Swing Headroom:
max_swing_pos = Vcc - Vc
max_swing_neg = Vc - Ve - 0.2 V
max_swing_pp = 2 × min(max_swing_pos, max_swing_neg)

Small-Signal Parameters:
VT = 26 mV (thermal voltage at 25°C)
r_e = VT / Ie (dynamic emitter resistance)
g_m = Ic / VT (transconductance)
r_π = β / g_m (base-emitter resistance)
Effective Collector Load:
RC,eff = RC || RL = (RC · RL) / (RC + RL)
Voltage Gain (mid-band):
Av = -RC,eff / (RE1 + r_e)
Solving for RE1 (from desired gain):
RE1 = RC,eff / |Av| - r_e
RE2 = RE,total - RE1
Input Impedance:
Rin_bias = R1 || R2 = (R1 · R2) / (R1 + R2)
Rin_base = r_π + (β + 1) · RE1
Rin_total = Rin_bias || Rin_base

Bypass Capacitor (with 10× safety margin):
CE ≥ 10 / (2π · fmin · RE2)
Actual -3dB Frequency:
f_3dB = 1 / (2π · CE · RE2)
Purpose: CE shorts RE2 at AC frequencies, leaving only RE1 in the gain equation. Use electrolytic capacitor (observe polarity: + to emitter).

Input Coupling Capacitor (with 10× safety margin):
Rin_input = Rsource + Rin_total
Cin ≥ 10 / (2π · fmin · Rin_input)
Output Coupling Capacitor (with 10× safety margin):
Cout ≥ 10 / (2π · fmin · RL)
Actual -3dB Frequencies:
f_3dB,in = 1 / (2π · Cin · Rin_input)
f_3dB,out = 1 / (2π · Cout · RL)
Purpose: Cin and Cout block DC while passing AC signals. They form high-pass filters with the circuit impedances. Use non-polarized (film or ceramic) capacitors.

Transistor DC Relationships:
Ic ≈ Ie (for β >> 1)
Ic = β · Ib
Vbe ≈ 0.65 V (silicon BJT at 25°C)
VT = kT/q ≈ 26 mV at 25°C
Active Region Conditions:
VCE > 0.2 V (minimum for active region)
VCE ≈ Vcc/2 (recommended for maximum swing)
Vb > Ve (base-emitter junction forward biased)
Vc > Vb (collector-base junction reverse biased)
Parallel Resistor Formula:
R1 || R2 = (R1 · R2) / (R1 + R2)