MOSFET/JFET Amplifier and Switch Calculator

Field-Effect Transistor Design and Analysis Tool

This tool covers two applications for an N-channel MOSFET or JFET: an amplifier stage (common-source or source-follower) designed from target operating point (ID, VDS), AC gain and coupling/bypass capacitor requirements, or a switch stage (low-side, and high-side with gate-drive notes) with on-resistance and power dissipation calculations. Amplifier designs can be verified in two additional modes: from measured node voltages and known resistors, or from resistor values alone (theoretical operating point and gain).

Configuration

Common Emitter NPN Amplifier Circuit

+Vcc R1 Vb R2 RC Vc Q1 RE1 Ve RE2 CE
DESIGN INPUTS

Complete Amplifier Design

Workflow: Specify all requirements below, then click "Calculate Complete Design" to get all component values and design parameters.
1System Requirements
For all capacitors
Typical: 50Ω (RF), 600Ω (audio), 0Ω (ideal)
Large (>100kΩ) if unloaded
2Operating Point & Device Selection
Typical: 1-10 mA for small-signal
Recommend: VDD/2

Verification and Analysis Tools

Mode 1: Calculate from Measured Voltages and Resistors

Enter measured voltages and resistor values. Calculator will compute operating point and gain.

Supply Voltage & Device

Measured Voltages

Circuit Resistors

Mode 2: Theoretical Calculation from Resistors (without measurements)

Enter resistor values and VDD. Calculator will predict operating point and gain using device parameters.

Supply Voltage & Device

Circuit Components

Calculation Formulas Reference

Required Voltage Gain:
|Av| = Vout,pp / Vin,pp

MOSFET Drain Current (Saturation Region):
ID = K × (VGS - Vth)²
where K = transconductance parameter (A/V²)
Vth = threshold voltage
JFET Drain Current (Saturation Region):
ID = IDSS × (1 - VGS/VP)²
where IDSS = saturation current at VGS=0
VP = pinch-off voltage (negative for N-channel)
Operating Point Voltages:
VS = 2 V (recommended for stability, MOSFET)
VD = VS + VDS,Q
VG = VS + VGS (MOSFET) or 0V (JFET self-bias)
Drain & Source Resistors:
RD = (VDD - VD) / ID
RS = VS / ID
MOSFET Voltage Divider (stiff divider):
VGS_required = Vth + √(ID / K)
VG = VS + VGS_required
I_divider = ID / 10 (for stiffness)
R2 = VG / I_divider
R1 = (VDD - VG) / I_divider
JFET Self-Bias:
VG = 0 V (gate grounded through RG)
VGS = -ID × RS (negative!)
RG = 1 MΩ (typical, gate leakage path)
Output Swing Headroom:
max_swing_pos = VDD - VD
max_swing_neg = VD - VS - 0.5 V (triode margin)
max_swing_pp = 2 × min(max_swing_pos, max_swing_neg)

MOSFET Transconductance:
gm = 2 × K × (VGS - Vth)
or equivalently: gm = 2 × √(K × ID)
Output resistance: rd ≈ ∞ (ideal)
JFET Transconductance:
gm = |(-2 × IDSS × (1 - VGS/VP)) / VP|
or: gm = 2 × √(K × ID) where K = IDSS / VP²
Output resistance: rd = large (typically 10kΩ - 1MΩ)
Effective Drain Load:
RD,eff = RD || RL = (RD × RL) / (RD + RL)
Common Source Voltage Gain:
Av = -gm × RD,eff / (1 + gm × RS_unbypassed)
With full bypass (RS_unbypassed = 0): Av = -gm × RD,eff
Negative sign indicates phase inversion
Source Follower Voltage Gain:
Av = (gm × RS) / (1 + gm × RS) ≈ 1
Non-inverting, unity gain buffer
Zout = 1 / gm (very low)
Solving for RS Split (Common Source):
RS_unbypassed = RD,eff / |Av| - 1 / gm
RS_bypassed = RS - RS_unbypassed
(RS_bypassed is bypassed with CS capacitor)
Input Impedance:
FET gate: Zin,gate ≈ ∞ (very high, 10¹² Ω)
MOSFET: Zin = R1 || R2 (limited by bias divider)
JFET: Zin = RG (typically 1 MΩ)

Source Bypass Capacitor (with 10× safety margin):
CS ≥ 10 / (2π × fmin × RS_bypassed)
where RS_bypassed is the portion of RS to be bypassed
Actual -3dB Frequency:
f_3dB = 1 / (2π × CS × RS_bypassed)
Purpose: CS shorts RS_bypassed at AC frequencies, reducing source degeneration and increasing gain. RS_unbypassed remains for stability and linearity. Use electrolytic capacitor (observe polarity: + to source).

Input Coupling Capacitor (with 10× safety margin):
Rin_input = Rsource + Rin_total
Cin ≥ 10 / (2π · fmin · Rin_input)
Output Coupling Capacitor (with 10× safety margin):
Cout ≥ 10 / (2π · fmin · RL)
Actual -3dB Frequencies:
f_3dB,in = 1 / (2π · Cin · Rin_input)
f_3dB,out = 1 / (2π · Cout · RL)
Purpose: Cin and Cout block DC while passing AC signals. They form high-pass filters with the circuit impedances. Use non-polarized (film or ceramic) capacitors.

FET Operating Regions:
MOSFET:
• Cutoff: VGS < Vth
• Triode: VGS > Vth AND VDS < (VGS - Vth)
• Saturation: VGS > Vth AND VDS ≥ (VGS - Vth)

JFET:
• Cutoff: VGS < VP
• Saturation: VGS > VP AND VDS ≥ (VGS - VP)
Recommended Operating Point:
VDS ≈ VDD / 2 (for maximum output swing)
VDS > 1 V (minimum for good saturation)
Overdrive (VGS - Vth) > 0.5 V (MOSFET, for stability)
Gate Current:
IG ≈ 0 (FET gate draws negligible current)
ID = IS (drain current equals source current)
Gate input capacitance: Ciss ≈ 50-500 pF (typical)
Useful Formulas:
Parallel resistors: R1 || R2 = (R1 × R2) / (R1 + R2)
Power dissipation: P = ID² × RDS (for switches)
Thermal voltage: VT = kT/q ≈ 26 mV at 25°C