Transformer-Coupled Driver Stage

BJT amplifier driving a transformer – DC isolation, impedance transformation, coupling quality, gain and output voltage

This calculator designs a common-emitter BJT stage feeding a transformer primary, in either series-feed (primary as the DC collector load) or parallel-feed (RFC supplies DC, primary AC-coupled via a coupling capacitor) topology. It computes the DC operating point, winding resistance drop, turns-ratio impedance transformation to the load, RFC/coupling-capacitor reactance requirements, and the resulting voltage gain and output level.

0Select feed topology

Series feed – primary is the collector load
DC bias current flows through the primary winding (most common for RF driver stages)
  • Transistor Q in common-emitter configuration
  • V_CC connects directly to the top of the primary winding L_p
  • Bottom of L_p connects to the collector – primary is the collector load
  • DC quiescent current I_C flows through the primary winding
  • Check: DC winding resistance R_w must be small (I_C × R_w << VCE)
  • RF signal is developed across the primary, transferred to secondary via coupling k
  • Secondary provides galvanic DC isolation – secondary DC bias is independent
  • Output taken from secondary across load R_load
  • Emitter resistor R_E with bypass cap C_E for bias stability
  • Base bias via R1/R2 divider; input via coupling cap C_in
Parallel feed – RFC supplies DC, primary is AC-coupled
DC and RF paths separated – no DC through transformer (better for wideband or high-power stages)
  • Transistor Q in common-emitter configuration
  • RFC (RF choke) connects V_CC to the collector – carries DC only
  • Primary winding L_p is AC-coupled to the collector via coupling capacitor C_c
  • C_c blocks DC from the primary: no DC bias current flows through L_p
  • Primary and secondary both fully isolated from DC supply
  • RFC impedance must satisfy: X_RFC ≥ 10 × n²·R_load at operating frequency
  • C_c reactance must satisfy: X_Cc ≤ n²·R_load / 10 at operating frequency
  • Allows independent biasing of primary and secondary circuits
  • Better saturation margin – no DC flux in transformer core

1Input parameters

Transistor and DC bias
Collector bias current
≈ VCC/2 for Class A
Primary DC resistance (series feed)
Previous stage output Z (for input matching check)
Transformer parameters
Measured or estimated
Typical: 0.85–0.99
Winding quality factor
Load and operating frequency
Input impedance of following stage
Tip: If the following stage is another BJT (β≈100, I_C≈5 mA):
R_in ≈ β × r_e = 100 × 5.2 Ω ≈ 520 Ω

Formula Reference

Turns ratio (primary to secondary):
n = N_p / N_s
n > 1: step-down (V_s < V_p, Z_p > Z_s)
n < 1: step-up (V_s > V_p, Z_p < Z_s)
n = 1: isolation only (no voltage/impedance transformation)
Secondary inductance from primary:
L_s = L_p / n² (for perfectly coupled transformer, k=1)
Mutual inductance: M = k · √(L_p · L_s) = k · L_p / n
Leakage inductances:
L_lk_p = (1 − k²) · L_p [primary leakage]
L_lk_s = (1 − k²) · L_s [secondary leakage]
Leakage limits high-frequency bandwidth
Core loss resistance (parallel model):
R_core = Q_T · X_Lp = Q_T · ω · L_p
(represents core hysteresis and eddy current losses)

Load impedance reflected to primary:
R_refl = n² · R_load (where n = N_p/N_s)
This is what the transistor collector "sees" as its AC load
Effective primary impedance (real transformer):
X_Lp = ω · L_p [magnetising reactance]
Z_primary = jX_Lp ‖ R_refl = jX_Lp · R_refl / (R_refl + jX_Lp)
|Z_primary| = X_Lp · R_refl / √(X_Lp² + R_refl²)
Coupling efficiency η:
η = |Z_primary| / R_refl = X_Lp / √(X_Lp² + R_refl²)
η → 1.0 when X_Lp >> R_refl (good coupling)
η = 0.71 when X_Lp = R_refl (3 dB coupling loss)
Design rule for good coupling:
X_Lp ≥ 5 · R_refl → η ≥ 0.98 (<0.2 dB loss)
X_Lp ≥ 3 · R_refl → η ≥ 0.95 (<0.5 dB loss)
X_Lp ≥ 1 · R_refl → η ≥ 0.71 (3 dB loss – marginal)
Insertion loss from finite L_p:
IL = 20 · log10(η) [dB, negative value]

Transistor transconductance:
g_m = I_C / V_T, V_T = 26 mV at 25 °C
g_m [mS] = I_C [mA] / 26
Voltage gain at primary (across Z_primary):
A_v_primary = g_m · |Z_primary|
Ideal (infinite L_p): A_v_ideal = g_m · R_refl = g_m · n² · R_load
Voltage gain at secondary:
A_v_secondary = A_v_primary / n (secondary = primary / turns ratio)
= g_m · |Z_primary| / n
Output voltage estimate (peak):
V_primary,pk = min(I_C · |Z_primary|, V_CE,Q − 0.2) · 0.9
V_secondary,pk = V_primary,pk / n [step-down, n>1]
V_secondary,pk = V_primary,pk · (1/n) = V_primary,pk / n
Power delivered to load:
V_sec,rms = V_sec,pk / √2
P_load = V_sec,rms² / R_load

Low-frequency −3 dB cutoff (magnetising inductance limit):
f_low = R_refl / (2π · L_p)
Below f_low: magnetising reactance X_Lp < R_refl → poor coupling
High-frequency −3 dB cutoff (leakage inductance limit):
L_lk = (1 − k²) · L_p [primary-referred total leakage]
f_high = R_refl / (2π · L_lk)
Above f_high: leakage impedance X_lk > R_refl → coupling degrades
Usable bandwidth ratio:
f_high / f_low = L_p / L_lk = 1 / (1 − k²)
k=0.95: BW ratio = 1/(1−0.9025) ≈ 10×
k=0.99: BW ratio = 1/(1−0.9801) ≈ 50×
For the operating frequency f to be well within bandwidth:
f_low << f << f_high
Requirement: f ≥ 3 × f_low and f ≤ f_high / 3

What is galvanically isolated:
Primary DC bias (V_CE, I_C) and secondary DC bias are completely independent
Each stage can use different V_CC, different I_C, different V_CE
Series feed: DC through primary winding
DC voltage at collector: V_C = V_CC − I_C · R_w
(R_w = DC resistance of primary winding, typically < 5 Ω for RF transformers)
V_CE = V_C − V_E = (V_CC − I_C·R_w) − I_E·R_E
Secondary is completely free of primary DC
Parallel feed: no DC through primary winding
RFC carries all DC: V_C = V_CC (no voltage drop from winding)
C_c blocks DC from transformer primary
No DC magnetisation in core → better for saturation-limited cores
Core saturation check (series feed only):
DC flux: Φ_DC = L_p · I_C / N_p
For no saturation: Φ_DC < Φ_sat (core material specific)
Rule of thumb: L_p · I_C < 0.1 · (N_p · A_core · B_sat)
For air-core transformers: no saturation risk
Magnetising current (AC, flowing in primary):
I_mag,pk = V_primary,pk / (ω · L_p)
Should be << I_C to avoid distortion of operating point
Rule of thumb: I_mag,pk < 0.1 · I_C

Operating point:
g_m = I_C / V_T = I_C / 0.026 [S]
r_e = V_T / I_C = 26 mV / I_C [Ω]
r_π = β / g_m [Ω]
Emitter stabilisation:
V_E = max(1.0 V, 0.1 · V_CC)
V_B = V_E + 0.65 V
R_E = V_E / I_E, I_E ≈ I_C · (1 + 1/β)
Base voltage divider:
I_div = 10 · I_B = 10 · I_C / β
R₁ = (V_CC − V_B) / I_div
R₂ = V_B / I_div
Series feed – collector voltage:
V_C = V_CC − I_C · R_w (R_w = winding DC resistance)
Effective V_CE = V_C − V_E